This invention is in the field of integrated circuit manufacture. Embodiments of this invention are directed to the physical layout of polysilicon conductors at locations of integrated circuits away from active transistor regions.
Advances in semiconductor technology in recent years have enabled the shrinking of minimum device feature sizes, such as metal-oxide-semiconductor (MOS) transistor gates, into the deep sub-micron range. For example, according to some advanced manufacturing technologies as of this date, the target MOS transistor gate width after etch is on the order of 30 nm. Because of the strong effect of transistor channel length on the overall performance of the integrated circuit, as well as on the chip area required for fabrication of a given circuit function, the dimension of transistor gate width is typically the smallest patterned feature size in the integrated circuit. As well known in the art, the dimension of the MOS transistor gate width is thus often referred to as the “critical dimension”, or “CD”.
For some years now, this critical dimension has approached (if not gone beyond) the limits of optical photolithography, considering that the desired gate widths are much smaller than the wavelength of light in the “deep ultraviolet” band that is used in the photolithography of these features. The masked patterning of features having dimensions smaller than the wavelength of the incident light has raised many complex issues in the photolithography process. So-called “resolution enhancement techniques” (or “RETs”) have been developed in recent years to extend the capability of optical photolithography to its ultimate fundamental resolution limits.
Off-axis illumination (“OAI”) is one RET that is now commonly used in the industry for the photolithographic patterning of critical dimensions in the deep sub-micron range. In general, according to the OAI technique, the light illuminating the mask (i.e., reticle) is constrained to components at an oblique angle to the plane of the mask. For example, OAI is achieved by exposure of the photomask plane through a centrally-obstructed aperture, which blocks on-axis light components yet passes oblique components to the mask plane. This illumination enables higher order pattern information to be projected onto the image plane (i.e., the surface of the photoresist) than would otherwise result from incident light normal to the mask plane. Selection of the aperture allows the angle of diffraction to match a certain feature pitch (i.e., line width plus spacing). This effect of OAI is not present, however, for feature pitches outside of the preferred pitch; indeed, for some pitches, the process margin is severely reduced by OAI. As such, modern integrated circuit layouts suitable for use in connection with OAI constrain the feature pitch to a specified range, in order to take advantage of the higher order pattern information transfer and to avoid the degraded process margin. In addition, these layouts typically constrain the orientation of critical dimension elements to a single direction, to the greatest extent practicable for the circuit function.
Another RET known in the art is the use of sub-resolution assist features (SRAFs) adjacent to and spaced from critical dimension features such as transistor gates. Sub-resolution assist features are photomask features that have a dimension below the minimum that can be successfully printed by the photolithography process. In other words, even though an SRAF is present (and “visible”) on the reticle, the SRAF is so narrow that it will not itself print on the photoresist after exposure. However, an SRAF that is properly spaced from a true critical dimension feature (i.e., one that is intended to be printed) provides a diffraction effect similar to an adjacent full-width feature, resulting in proper focus of the desired critical dimension feature. In this manner, a critical dimension feature at an edge of an array, or in some other way farther from the next similar feature by more than the regular spacing, can be properly patterned by use of an SRAF at the same resolution as if the feature were located within the array of regular pitch features.
These resolution enhancement techniques of off-axis illumination and sub-resolution assist features have been incorporated into the photolithography of logic arrays and memory arrays, for gate width features as small as on the order of 45 nm as patterned. So long as the polysilicon layout can be restrained to the preferred orientation, and the pitch constraints obeyed, control and resolution of features at these dimensions can be quite good. However, in many integrated circuits, polysilicon elements are not used only for transistor gates or other regular structures oriented only in the preferred direction. Rather, these integrated circuits avoid the addition of yet another level of metal conductors by using polysilicon conductors as interconnects. Such polysilicon interconnects necessarily extend over isolation oxide, such as field oxide and trench isolation oxide structures, and often must run in a direction perpendicular to the preferred orientation for photolithography. To minimize chip area, these “field poly” structures are patterned and etched to dimensions on the same order as the critical dimension used for transistor gates. But because the regularity of pitch and preferred orientation rules cannot be obeyed for these field poly interconnects and other structures, resolution and critical dimension control is rendered difficult.